The code is generated by the IBM C compiler
and unlikely to be wrong.
I am using 64-bit registers.
And the Hercules code is this:
int r1; /* Register number */
int opcd; /* Opcode */
U16 i2; /* 16-bit operand values */
RI0(inst, regs, r1, opcd, i2);
regs->GR_LHH(r1) |= i2;
/* Set condition code according to result */
regs->psw.cc = regs->GR_LHH(r1) ? 1 : 0;
} /* end DEF_INST(or_immediate_low_high) */
ie it only changes the register, not a
Regardless, I tried changing this:
in my test program, to this:
and I still get a S0C1.
I used 2 instead of 1 because of the
nature of my test program (ie for
testing I just modify mvsstart rather
than executing the z/OS program).
---In email@example.com, <***@...> wrote :
Oh ... also it just occurred to me ... the R must be 64-bits long. Are you using 64 or 32 bit registers?
On Sun, Oct 14, 2018 at 7:12 AM Joe Monk <***@... mailto:***@...> wrote:
I think youre getting this because youre trying to use register 0 to point to storage in an immediate operation.
Register 0 cant be used as a base or index register. So your operation is: Take the value pointed at by register 0 and OR it with 10000000, and then store that back at the address located in R0. But 0 in a register position means no base!
Try a different register and see if the problem goes away...
On Sun, Oct 14, 2018 at 5:10 AM ***@... mailto:***@... [hercules-390] <firstname.lastname@example.org mailto:email@example.com> wrote:
I have been working on getting PDPCLIB
to work on IBM C (again), and I have been
able to build a module, but it is not
working as expected on z/OS (just
returns RC 12).
I would like to debug it on MVS/380, and
have the load module loaded, but unlike
on z/OS, I am getting a S0C1, on this
which is being used to set the top bit
of the 32-bit register as the end of
I can't explain why OILH is getting a S0C1 but
other z/Arch instructions like SGR are working
In both cases the instructions are defined as:
which I have overridden with:
#define GENx___x___x900 GENx37Xx___x900
to enable them all.
For both SGR and OILH I have enabled them
in esame.c with this code:
In opcode.c I have enabled the a5xx routines with:
#if defined(FEATURE_ESAME) || defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_S380)
I've run out of ideas.
I'm using Hercules/380 which is a modified
version of standard Hercules 3.07.
Any idea what else I need to enable to allow
the OILH instruction to work?