Discussion:
OILH
(too old to reply)
kerravon86@yahoo.com.au [hercules-390]
2018-10-14 10:09:42 UTC
Permalink
I have been working on getting PDPCLIB
to work on IBM C (again), and I have been
able to build a module, but it is not
working as expected on z/OS (just
returns RC 12).

I would like to debug it on MVS/380, and
have the load module loaded, but unlike
on z/OS, I am getting a S0C1, on this
instruction:

X'A50A8000'

which is:

OILH 0,-32768

which is being used to set the top bit
of the 32-bit register as the end of
parameter list.

I can't explain why OILH is getting a S0C1 but
other z/Arch instructions like SGR are working
fine.

In both cases the instructions are defined as:

GENx___x___x900

which I have overridden with:

#ifdef FEATURE_S380
#define GENx___x___x900 GENx37Xx___x900

to enable them all.

For both SGR and OILH I have enabled them
in esame.c with this code:

#if defined(FEATURE_S380)
#define FEATURE_ESAME
#endif

In opcode.c I have enabled the a5xx routines with:

#if defined(FEATURE_ESAME) || defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_S380)
DEF_INST(execute_a5xx)
{
regs->ARCH_DEP(opcode_a5xx)[inst[1]](inst, regs);
}


I've run out of ideas.

I'm using Hercules/380 which is a modified
version of standard Hercules 3.07.

Any idea what else I need to enable to allow
the OILH instruction to work?

Thanks. Paul.
Joe Monk joemonk64@gmail.com [hercules-390]
2018-10-14 12:12:06 UTC
Permalink
I think youre getting this because youre trying to use register 0 to point
to storage in an immediate operation.

Register 0 cant be used as a base or index register. So your operation is:
Take the value pointed at by register 0 and OR it with 10000000, and then
store that back at the address located in R0. But 0 in a register position
means no base!

Try a different register and see if the problem goes away...

Joe
Post by ***@yahoo.com.au [hercules-390]
I have been working on getting PDPCLIB
to work on IBM C (again), and I have been
able to build a module, but it is not
working as expected on z/OS (just
returns RC 12).
I would like to debug it on MVS/380, and
have the load module loaded, but unlike
on z/OS, I am getting a S0C1, on this
X'A50A8000'
OILH 0,-32768
which is being used to set the top bit
of the 32-bit register as the end of
parameter list.
I can't explain why OILH is getting a S0C1 but
other z/Arch instructions like SGR are working
fine.
GENx___x___x900
#ifdef FEATURE_S380
#define GENx___x___x900 GENx37Xx___x900
to enable them all.
For both SGR and OILH I have enabled them
#if defined(FEATURE_S380)
#define FEATURE_ESAME
#endif
#if defined(FEATURE_ESAME) || defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_S380)
DEF_INST(execute_a5xx)
{
regs->ARCH_DEP(opcode_a5xx)[inst[1]](inst, regs);
}
I've run out of ideas.
I'm using Hercules/380 which is a modified
version of standard Hercules 3.07.
Any idea what else I need to enable to allow
the OILH instruction to work?
Thanks. Paul.
Joe Monk joemonk64@gmail.com [hercules-390]
2018-10-14 12:50:40 UTC
Permalink
Oh ... also it just occurred to me ... the R must be 64-bits long. Are you
using 64 or 32 bit registers?

Joe
Post by Joe Monk ***@gmail.com [hercules-390]
I think youre getting this because youre trying to use register 0 to point
to storage in an immediate operation.
Take the value pointed at by register 0 and OR it with 10000000, and then
store that back at the address located in R0. But 0 in a register position
means no base!
Try a different register and see if the problem goes away...
Joe
Post by ***@yahoo.com.au [hercules-390]
I have been working on getting PDPCLIB
to work on IBM C (again), and I have been
able to build a module, but it is not
working as expected on z/OS (just
returns RC 12).
I would like to debug it on MVS/380, and
have the load module loaded, but unlike
on z/OS, I am getting a S0C1, on this
X'A50A8000'
OILH 0,-32768
which is being used to set the top bit
of the 32-bit register as the end of
parameter list.
I can't explain why OILH is getting a S0C1 but
other z/Arch instructions like SGR are working
fine.
GENx___x___x900
#ifdef FEATURE_S380
#define GENx___x___x900 GENx37Xx___x900
to enable them all.
For both SGR and OILH I have enabled them
#if defined(FEATURE_S380)
#define FEATURE_ESAME
#endif
#if defined(FEATURE_ESAME) || defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_S380)
DEF_INST(execute_a5xx)
{
regs->ARCH_DEP(opcode_a5xx)[inst[1]](inst, regs);
}
I've run out of ideas.
I'm using Hercules/380 which is a modified
version of standard Hercules 3.07.
Any idea what else I need to enable to allow
the OILH instruction to work?
Thanks. Paul.
kerravon86@yahoo.com.au [hercules-390]
2018-10-15 00:38:08 UTC
Permalink
Hi Joe.

The code is generated by the IBM C compiler
and unlikely to be wrong.

I am using 64-bit registers.

And the Hercules code is this:

DEF_INST(or_immediate_low_high)
{
int r1; /* Register number */
int opcd; /* Opcode */
U16 i2; /* 16-bit operand values */

RI0(inst, regs, r1, opcd, i2);

regs->GR_LHH(r1) |= i2;

/* Set condition code according to result */
regs->psw.cc = regs->GR_LHH(r1) ? 1 : 0;

} /* end DEF_INST(or_immediate_low_high) */


ie it only changes the register, not a
memory address.

Regardless, I tried changing this:

DC X'A50A8000'

in my test program, to this:

DC X'A52A8000'

and I still get a S0C1.

I used 2 instead of 1 because of the
nature of my test program (ie for
testing I just modify mvsstart rather
than executing the z/OS program).

BFN. Paul.



---In hercules-***@yahoogroups.com, <***@...> wrote :

Oh ... also it just occurred to me ... the R must be 64-bits long. Are you using 64 or 32 bit registers?

Joe


On Sun, Oct 14, 2018 at 7:12 AM Joe Monk <***@... mailto:***@...> wrote:

I think youre getting this because youre trying to use register 0 to point to storage in an immediate operation.


Register 0 cant be used as a base or index register. So your operation is: Take the value pointed at by register 0 and OR it with 10000000, and then store that back at the address located in R0. But 0 in a register position means no base!


Try a different register and see if the problem goes away...


Joe



On Sun, Oct 14, 2018 at 5:10 AM ***@... mailto:***@... [hercules-390] <hercules-***@yahoogroups.com mailto:hercules-***@yahoogroups.com> wrote:

I have been working on getting PDPCLIB
to work on IBM C (again), and I have been
able to build a module, but it is not
working as expected on z/OS (just
returns RC 12).

I would like to debug it on MVS/380, and
have the load module loaded, but unlike
on z/OS, I am getting a S0C1, on this
instruction:

X'A50A8000'

which is:

OILH 0,-32768

which is being used to set the top bit
of the 32-bit register as the end of
parameter list.

I can't explain why OILH is getting a S0C1 but
other z/Arch instructions like SGR are working
fine.

In both cases the instructions are defined as:

GENx___x___x900

which I have overridden with:

#ifdef FEATURE_S380
#define GENx___x___x900 GENx37Xx___x900

to enable them all.

For both SGR and OILH I have enabled them
in esame.c with this code:

#if defined(FEATURE_S380)
#define FEATURE_ESAME
#endif

In opcode.c I have enabled the a5xx routines with:

#if defined(FEATURE_ESAME) || defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_S380)
DEF_INST(execute_a5xx)
{
regs->ARCH_DEP(opcode_a5xx)[inst[1]](inst, regs);
}

I've run out of ideas.

I'm using Hercules/380 which is a modified
version of standard Hercules 3.07.

Any idea what else I need to enable to allow
the OILH instruction to work?

Thanks. Paul.
Mike Schwab Mike.A.Schwab@gmail.com [hercules-390]
2018-10-15 00:47:20 UTC
Permalink
IBM MVS Abend S0C1 means the OPERATION CODE is not recognized. Need
to add the OP Code to the emulator.
Post by ***@yahoo.com.au [hercules-390]
Hi Joe.
The code is generated by the IBM C compiler
and unlikely to be wrong.
I am using 64-bit registers.
DEF_INST(or_immediate_low_high)
{
int r1; /* Register number */
int opcd; /* Opcode */
U16 i2; /* 16-bit operand values */
RI0(inst, regs, r1, opcd, i2);
regs->GR_LHH(r1) |= i2;
/* Set condition code according to result */
regs->psw.cc = regs->GR_LHH(r1) ? 1 : 0;
} /* end DEF_INST(or_immediate_low_high) */
ie it only changes the register, not a
memory address.
DC X'A50A8000'
DC X'A52A8000'
and I still get a S0C1.
I used 2 instead of 1 because of the
nature of my test program (ie for
testing I just modify mvsstart rather
than executing the z/OS program).
BFN. Paul.
Oh ... also it just occurred to me ... the R must be 64-bits long. Are you using 64 or 32 bit registers?
Joe
I think youre getting this because youre trying to use register 0 to point to storage in an immediate operation.
Register 0 cant be used as a base or index register. So your operation is: Take the value pointed at by register 0 and OR it with 10000000, and then store that back at the address located in R0. But 0 in a register position means no base!
Try a different register and see if the problem goes away...
Joe
I have been working on getting PDPCLIB
to work on IBM C (again), and I have been
able to build a module, but it is not
working as expected on z/OS (just
returns RC 12).
I would like to debug it on MVS/380, and
have the load module loaded, but unlike
on z/OS, I am getting a S0C1, on this
X'A50A8000'
OILH 0,-32768
which is being used to set the top bit
of the 32-bit register as the end of
parameter list.
I can't explain why OILH is getting a S0C1 but
other z/Arch instructions like SGR are working
fine.
GENx___x___x900
#ifdef FEATURE_S380
#define GENx___x___x900 GENx37Xx___x900
to enable them all.
For both SGR and OILH I have enabled them
#if defined(FEATURE_S380)
#define FEATURE_ESAME
#endif
#if defined(FEATURE_ESAME) || defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_S380)
DEF_INST(execute_a5xx)
{
regs->ARCH_DEP(opcode_a5xx)[inst[1]](inst, regs);
}
I've run out of ideas.
I'm using Hercules/380 which is a modified
version of standard Hercules 3.07.
Any idea what else I need to enable to allow
the OILH instruction to work?
Thanks. Paul.
------------------------------------
------------------------------------
http://groups.yahoo.com/group/hercules-390
http://www.hercules-390.org
------------------------------------
Yahoo Groups Links
--
Mike A Schwab, Springfield IL USA
Where do Forest Rangers go to get away from it all?
Mike Stramba mikestramba@gmail.com [hercules-390]
2018-10-15 03:34:50 UTC
Permalink
OILH is an RI format instruction (register-and-immediate operation
and an extended op-code field) POP (twelfth edition) pg 7-312

The R1 field in the instruction is not a "point to storage" register.

X'A50A8000' OILH 0,-32768 .. works perfectly as expected with
ARCHMODE esame or z/Arch

There are no register restrictions mentioned in the POP for the OILH
instruction

Mike
Post by Joe Monk ***@gmail.com [hercules-390]
I think youre getting this because youre trying to use register 0 to point
to storage in an immediate operation.
Take the value pointed at by register 0 and OR it with 10000000, and then
store that back at the address located in R0. But 0 in a register position
means no base!
Try a different register and see if the problem goes away...
Joe
Post by ***@yahoo.com.au [hercules-390]
I have been working on getting PDPCLIB
to work on IBM C (again), and I have been
able to build a module, but it is not
working as expected on z/OS (just
returns RC 12).
I would like to debug it on MVS/380, and
have the load module loaded, but unlike
on z/OS, I am getting a S0C1, on this
X'A50A8000'
OILH 0,-32768
which is being used to set the top bit
of the 32-bit register as the end of
parameter list.
I can't explain why OILH is getting a S0C1 but
other z/Arch instructions like SGR are working
fine.
GENx___x___x900
#ifdef FEATURE_S380
#define GENx___x___x900 GENx37Xx___x900
to enable them all.
For both SGR and OILH I have enabled them
#if defined(FEATURE_S380)
#define FEATURE_ESAME
#endif
#if defined(FEATURE_ESAME) || defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_S380)
DEF_INST(execute_a5xx)
{
regs->ARCH_DEP(opcode_a5xx)[inst[1]](inst, regs);
}
I've run out of ideas.
I'm using Hercules/380 which is a modified
version of standard Hercules 3.07.
Any idea what else I need to enable to allow
the OILH instruction to work?
Thanks. Paul.
Joe Monk joemonk64@gmail.com [hercules-390]
2018-10-15 10:36:50 UTC
Permalink
Yep, thanks. :)

I was misreading a part from Chapter 2.

Joe
Post by Mike Stramba ***@gmail.com [hercules-390]
OILH is an RI format instruction (register-and-immediate operation
and an extended op-code field) POP (twelfth edition) pg 7-312
The R1 field in the instruction is not a "point to storage" register.
X'A50A8000' OILH 0,-32768 .. works perfectly as expected with
ARCHMODE esame or z/Arch
There are no register restrictions mentioned in the POP for the OILH
instruction
Mike
Post by Joe Monk ***@gmail.com [hercules-390]
I think youre getting this because youre trying to use register 0 to
point
Post by Joe Monk ***@gmail.com [hercules-390]
to storage in an immediate operation.
Register 0 cant be used as a base or index register. So your operation
Take the value pointed at by register 0 and OR it with 10000000, and then
store that back at the address located in R0. But 0 in a register
position
Post by Joe Monk ***@gmail.com [hercules-390]
means no base!
Try a different register and see if the problem goes away...
Joe
Post by ***@yahoo.com.au [hercules-390]
I have been working on getting PDPCLIB
to work on IBM C (again), and I have been
able to build a module, but it is not
working as expected on z/OS (just
returns RC 12).
I would like to debug it on MVS/380, and
have the load module loaded, but unlike
on z/OS, I am getting a S0C1, on this
X'A50A8000'
OILH 0,-32768
which is being used to set the top bit
of the 32-bit register as the end of
parameter list.
I can't explain why OILH is getting a S0C1 but
other z/Arch instructions like SGR are working
fine.
GENx___x___x900
#ifdef FEATURE_S380
#define GENx___x___x900 GENx37Xx___x900
to enable them all.
For both SGR and OILH I have enabled them
#if defined(FEATURE_S380)
#define FEATURE_ESAME
#endif
#if defined(FEATURE_ESAME) || defined(FEATURE_ESAME_N3_ESA390) ||
defined(FEATURE_S380)
DEF_INST(execute_a5xx)
{
regs->ARCH_DEP(opcode_a5xx)[inst[1]](inst, regs);
}
I've run out of ideas.
I'm using Hercules/380 which is a modified
version of standard Hercules 3.07.
Any idea what else I need to enable to allow
the OILH instruction to work?
Thanks. Paul.
Harold Grovesteen h.grovsteen@tx.rr.com [hercules-390]
2018-10-14 15:13:43 UTC
Permalink
I do not know what changes have been made for MVS380 to Hercules.

However, in native Hercules, instructions for GEN x37X requires the
instruction to be enabled via the s37x.c module.  The instruction
tables for s370 are modified during initialization by the module.

See if the A5 instruction is enabled by the s37x.c module.  If not, add
it.  I believe this may be why you are getting an operation exception.

The current content of the s37x.c module in Hyperion does not include
A5.

Harold
Post by ***@yahoo.com.au [hercules-390]
I have been working on getting PDPCLIB
to work on IBM C (again), and I have been
able to build a module, but it is not
working as expected on z/OS (just
returns RC 12).
I would like to debug it on MVS/380, and
have the load module loaded, but unlike
on z/OS, I am getting a S0C1, on this
X'A50A8000'
OILH  0,-32768
which is being used to set the top bit
of the 32-bit register as the end of
parameter list.
I can't explain why OILH is getting a S0C1 but
other z/Arch instructions like SGR are working
fine.
GENx___x___x900
#ifdef FEATURE_S380
#define GENx___x___x900 GENx37Xx___x900
to enable them all.
For both SGR and OILH I have enabled them
#if defined(FEATURE_S380)
#define FEATURE_ESAME
#endif
#if defined(FEATURE_ESAME) || defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_S380)
DEF_INST(execute_a5xx)
{
    regs->ARCH_DEP(opcode_a5xx)[inst[1]](inst, regs);
}
I've run out of ideas.
I'm using Hercules/380 which is a modified
version of standard Hercules 3.07.
Any idea what else I need to enable to allow
the OILH instruction to work?
Thanks. Paul.
------------------------------------
------------------------------------
  http://groups.yahoo.com/group/hercules-390
  http://www.hercules-390.org
------------------------------------
Yahoo Groups Links
kerravon86@yahoo.com.au [hercules-390]
2018-10-15 00:25:22 UTC
Permalink
Post by Harold Grovesteen ***@tx.rr.com [hercules-390]
However, in native Hercules, instructions for GEN x37X requires the
instruction to be enabled via the s37x.c module. The instruction
tables for s370 are modified during initialization by the module.
Hi Harold. Thanks for your reply. s37x.c
doesn't exist in Hercules 3.07 or even
3.13. Do you know what the equivalent
is in there? I took a look at the Hyperion
code:

https://github.com/hercules-390/hyperion/blob/master/s37x.c

but I can't match that code to anything
in the 3.07 code.

Thanks. Paul.
kerravon86@yahoo.com.au [hercules-390]
2018-10-15 02:00:53 UTC
Permalink
I stumbled across a fix by copying some
z900 code to s370 as per this:

C:\devel\hercules>cvs diff -l
cvs diff: Diffing .
Index: opcode.c
===================================================================
RCS file: c:\cvsroot/hercules/opcode.c,v
retrieving revision 1.14
diff -r1.14 opcode.c
2032c2032,2033
< s370_opcode_a5xx [i] = v_opcode_a5xx [i][ARCH_370];
---
s370_opcode_a5xx [i] = opcode_a5xx [i&0x0F][ARCH_370];
/* s370_opcode_a5xx [i] = v_opcode_a5xx [i][ARCH_370]; */
C:\devel\hercules>


I don't know what that's about though.

But now OILH is working as expected.

Thanks all for your responses.

BFN. Paul.
kerravon86@yahoo.com.au [hercules-390]
2018-10-15 13:05:46 UTC
Permalink
Post by ***@yahoo.com.au [hercules-390]
I stumbled across a fix by copying some
s370_opcode_a5xx [i] = opcode_a5xx [i&0x0F][ARCH_370];
/* s370_opcode_a5xx [i] = v_opcode_a5xx [i][ARCH_370]; */
I don't know what that's about though.
I think I know what that is about now. The
first nibble after the x'a5' is the register,
so we need to repeat the values 16 times
for each register. But we have a single
source table, which is referenced with
the "i & 0x0f".

BFN. Paul.
Harold Grovesteen h.grovsteen@tx.rr.com [hercules-390]
2018-10-15 15:11:06 UTC
Permalink
Yes.  This is exactly what is needed.  The s37x.c module has a bunch of
statements like this.

Harold
Post by ***@yahoo.com.au [hercules-390]
Post by ***@yahoo.com.au [hercules-390]
I stumbled across a fix by copying some
s370_opcode_a5xx [i] = opcode_a5xx [i&0x0F][ARCH_370];
/* s370_opcode_a5xx [i] = v_opcode_a5xx [i][ARCH_370]; */
I don't know what that's about though.
I think I know what that is about now. The
first nibble after the x'a5' is the register,
so we need to repeat the values 16 times
for each register. But we have a single
source table, which is referenced with
the "i & 0x0f".
BFN. Paul.
I would be surprised that you need to be concerned about the first
register.  If 900 and 390 do not, 370 should not iether.  Experience
will dictate.

Harold

Loading...